Digital processors, such as microprocessors, use a computer memory subsystem to store data and processor instructions. Some processors communicate directly with memory, and others use a dedicated controller chip, often part of a “chipset,” to access memory.
Conventional computer memory subsystems are often implemented using memory modules. Referring to the computing system 100 shown in FIG. 1, a processor 120 communicates across a front-side bus 125 with a memory controller/hub (MCH) 130 that couples the processor 120 to various peripherals. One of these peripherals is system memory, shown as a memory module MM0. Although memory need not be arranged on such a module in every system, modules are used in many systems to allow memory expansion by replacing a module with a larger-capacity module and/or adding additional modules (not shown) in additional memory slots. When connected, memory module MM0 is addressed from MCH 130 whenever MCH 130 asserts appropriate signals on an Address/Command (ADD/CMD) bus 150. Data transfers between MCH 130 and one of the memory modules occur on a data bus 140.
Typically, memory modules are built using a plurality of semiconductor memory devices, with each individual device storing a portion of each data word stored on the module. For instance, memory module MM0 shows five Dynamic Random-Access Memory (DRAM) devices, DRAM0 to DRAM4. Each DRAM device receives the same address and command signals from ADD/CMD bus 150. Each DRAM device connects to a subset of the signal (DQn) lines making up the data bus 140, with DRAM0 connecting to sixteen bus lines DQ0-DQ15, DRAM1 connecting to DQ16-DQ31, DRAM2 connecting to DQ32-DQ47, DRAM3 connecting to DQ48-DQ63, and DRAM4 connecting to DQ64-DQ71. Thus when 72 bits of data are transferred across data bus 140 during a data cycle, each DRAM is responsible for 16 of those bits, except for DRAM4, which is responsible for eight bits (typically the other eight DQn inputs of DRAM4 are simply unconnected and half of DRAM4 is inaccessible). Each DRAM stores its assigned portion of the 72-bit word in the same chip location as each other DRAM stores its portion of the 72-bit word.
In the FIG. 1 example, the size of each addressable data word is 72 bits. 64 of those bits are used to store data. The additional eight bits are used to store Error Correction Coding (ECC) information corresponding to the 64 bits of data with the same address. For instance, DRAM4 can be dedicated to ECC storage, and DQ64-DQ71 are then used to store and retrieve ECC information. Other systems may use other bus widths, with 36 bits also being common, the bus divided into 32 data bit lanes and 4 ECC bit lanes.
Many current memory devices and controllers offer a burst mode that allows multiple sequentially stored data words to be accessed together with a single command. FIG. 2 shows a timing diagram for a 16-word burst mode data transfer using the ECC memory module MM0 of FIG. 1. MCH 130 supplies module MM0 with a starting address and a burst mode 16 read or write command. When the command is a read command, the DRAMs on module MM0 each read the data storage cells connected to a word line containing the starting address, and then drive the data from the starting address and the fifteen consecutive following addresses on data bus 140 over sixteen consecutive data cycles. When the command is a write command, MCH 130 supplies write data over sixteen consecutive data cycles, which the DRAMs on module MM0 receive, buffer, and then write to consecutive memory locations in a word line, starting at the starting address.
DRAM4 acts just like all other DRAMs during these burst commands, and need not be aware that its data may be used to perform an ECC function on the data stored in DRAM0 to DRAM3. For instance, during time slot T0, data “A” and ECC data “A” are transmitted, where “A” represents data at a starting address specified by MCH 130. During time slot T1, data “B” and ECC data “B” are transmitted, where “B” represents data at the address consecutively following the “A” address.
Not all systems use ECC protection as described above, because ECC protection requires a wider data bus and usually an extra memory chip per memory rank (e.g., DRAM4 and DQ64-DQ71 would not be needed in a 64-bit non-ECC system). Further, ECC generally increases latency (due to the error-checking function) and power consumption (due to the extra chip required). Non-ECC systems otherwise function as described above, except, e.g., the memory controller would trust the data integrity of the data received from DRAM0-DRAM3 in a read operation. Thus ECC and non-ECC memory modules are not interchangeable. Currently, more non-ECC systems are produced than ECC systems, primarily due to the drawbacks listed above.